The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
For example, the scaling down of a fin field effect transistor (FinFET) faces challenges of a stress relaxation of a channel between a source and a drain of the FinFET due to a finite length of a fin of the FinFET. The channel relaxation reduces channel stress and further reduces mobility of a charge moving in the channel. The low mobility of the charge moving in the change further reduces a performance of the FinFET. Accordingly, what is needed is a device for further scaling down of the FinFET.